BEGIN:VCALENDAR
PRODID:-//github.com/allenporter/ical//14.3.0//EN
VERSION:2.0
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c50c1-cd45-11f1-8f35-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260901T140000
DTEND;TZID=Europe/Paris:20260901T153000
SUMMARY:rattrapage Introduction au filtrage
DESCRIPTION:TD ELT4 TD02\nSA36 -C204\nMEGHDADI NEYSHABOURI Vahid\n14h00 - 
 15h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5452-cd45-11f1-bf84-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260907T100000
DTEND;TZID=Europe/Paris:20260907T113000
SUMMARY:Projet - gestion 1h30
DESCRIPTION:CM AET5 CM01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n10h00 - 11h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5621-cd45-11f1-9988-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260909T080000
DTEND;TZID=Europe/Paris:20260909T093000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c57c4-cd45-11f1-9fa9-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260910T150000
DTEND;TZID=Europe/Paris:20260910T153000
SUMMARY:Projet - gestion 30m
DESCRIPTION:CM AET5 CM01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 15h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5976-cd45-11f1-ad0c-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260910T133000
DTEND;TZID=Europe/Paris:20260910T150000
SUMMARY:Mise en œuvre d'un réseau de capteurs (CM01)
DESCRIPTION:CM AET5 CM01\nSA36 -C207\nMEGHDADI NEYSHABOURI Vahid\n13h30 - 
 15h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5b07-cd45-11f1-b12a-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260911T093000
DTEND;TZID=Europe/Paris:20260911T110000
SUMMARY:Mise en œuvre d'un réseau de capteurs (CM01)
DESCRIPTION:CM AET5 CM01\nSA36 -C207\nMEGHDADI NEYSHABOURI Vahid\n09h30 - 
 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5c94-cd45-11f1-bb42-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260916T163000
DTEND;TZID=Europe/Paris:20260916T180000
SUMMARY:Réunion Projet
DESCRIPTION:CM ELT5 CM01\nSA100 -B4.1 Ex-biblio\nMEGHDADI NEYSHABOURI 
 Vahid\n16h30 - 18h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c5ebd-cd45-11f1-8f0c-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260916T150000
DTEND;TZID=Europe/Paris:20260916T163000
SUMMARY:System On Chip (CM01)
DESCRIPTION:CM ELT5 CM01\nSA54 -II105\nMEGHDADI NEYSHABOURI Vahid\n15h00 - 
 16h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6101-cd45-11f1-9065-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260916T133000
DTEND;TZID=Europe/Paris:20260916T150000
SUMMARY:System On Chip (CM01)
DESCRIPTION:CM ELT5 CM01\nSA54 -II105\nMEGHDADI NEYSHABOURI Vahid\n13h30 - 
 15h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6369-cd45-11f1-84ca-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260916T093000
DTEND;TZID=Europe/Paris:20260916T110000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA54 -II105\nMEGHDADI NEYSHABOURI Vahid\n09h30 - 
 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6506-cd45-11f1-b64e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260917T133000
DTEND;TZID=Europe/Paris:20260917T153000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 15h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c671d-cd45-11f1-8e22-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260917T093000
DTEND;TZID=Europe/Paris:20260917T110000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c69a7-cd45-11f1-8eb9-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260918T170000
DTEND;TZID=Europe/Paris:20260918T180000
SUMMARY:Réunion Projet
DESCRIPTION:CM ELT5 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n17h00 - 18h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6b53-cd45-11f1-847d-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260918T093000
DTEND;TZID=Europe/Paris:20260918T123000
SUMMARY:System On Chip (TP03)
DESCRIPTION:TP ELT5 3G TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6cca-cd45-11f1-8c8b-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260921T093000
DTEND;TZID=Europe/Paris:20260921T123000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6e45-cd45-11f1-b3b5-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260922T150000
DTEND;TZID=Europe/Paris:20260922T180000
SUMMARY:Conception des circuits numériques TP (TP02)
DESCRIPTION:TP ELT4 TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 18h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c6fb5-cd45-11f1-b73f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260923T140000
DTEND;TZID=Europe/Paris:20260923T170000
SUMMARY:System On Chip (TP02)
DESCRIPTION:TP ELT5 3G TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 17h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c716d-cd45-11f1-93d6-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260924T093000
DTEND;TZID=Europe/Paris:20260924T123000
SUMMARY:System On Chip (TP01)
DESCRIPTION:TP ELT5 3G TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c72dc-cd45-11f1-a7c1-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260925T150000
DTEND;TZID=Europe/Paris:20260925T180000
SUMMARY:Conception des circuits numériques TP (TP04)
DESCRIPTION:TP ELT4 TP04\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 18h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7459-cd45-11f1-b21d-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260925T080000
DTEND;TZID=Europe/Paris:20260925T093000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7746-cd45-11f1-94e7-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260928T133000
DTEND;TZID=Europe/Paris:20260928T163000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7900-cd45-11f1-942d-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260929T150000
DTEND;TZID=Europe/Paris:20260929T180000
SUMMARY:System On Chip (TP02)
DESCRIPTION:TP ELT5 3G TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 18h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7a70-cd45-11f1-810f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20260929T093000
DTEND;TZID=Europe/Paris:20260929T123000
SUMMARY:System On Chip (TP01)
DESCRIPTION:TP ELT5 3G TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7be4-cd45-11f1-979a-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261001T093000
DTEND;TZID=Europe/Paris:20261001T123000
SUMMARY:Conception des circuits numériques TP (TP03)
DESCRIPTION:TP ELT4 TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7d5e-cd45-11f1-95fb-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261002T133000
DTEND;TZID=Europe/Paris:20261002T163000
SUMMARY:Conception des circuits numériques TP (TP04)
DESCRIPTION:TP ELT4 TP04\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c7ecc-cd45-11f1-aa7b-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261002T093000
DTEND;TZID=Europe/Paris:20261002T123000
SUMMARY:System On Chip (TP03)
DESCRIPTION:TP ELT5 3G TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8040-cd45-11f1-afb9-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261005T140000
DTEND;TZID=Europe/Paris:20261005T170000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 17h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c81b6-cd45-11f1-a045-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261005T093000
DTEND;TZID=Europe/Paris:20261005T110000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8341-cd45-11f1-baaa-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261006T133000
DTEND;TZID=Europe/Paris:20261006T163000
SUMMARY:Conception des circuits numériques TP (TP02)
DESCRIPTION:TP ELT4 TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c84ae-cd45-11f1-a956-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261007T140000
DTEND;TZID=Europe/Paris:20261007T170000
SUMMARY:System On Chip (TP03)
DESCRIPTION:TP ELT5 3G TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 17h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8615-cd45-11f1-b878-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261007T093000
DTEND;TZID=Europe/Paris:20261007T123000
SUMMARY:System On Chip (TP01)
DESCRIPTION:TP ELT5 3G TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c877b-cd45-11f1-b8fb-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261008T093000
DTEND;TZID=Europe/Paris:20261008T123000
SUMMARY:System On Chip (TP02)
DESCRIPTION:TP ELT5 3G TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c88f8-cd45-11f1-92ef-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261012T150000
DTEND;TZID=Europe/Paris:20261012T153000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 15h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8a93-cd45-11f1-8da4-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261012T140000
DTEND;TZID=Europe/Paris:20261012T150000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP AET5 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 15h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8c02-cd45-11f1-9f5f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261021T080000
DTEND;TZID=Europe/Paris:20261021T093000
SUMMARY:Conception des circuits numériques cours (CM01)
DESCRIPTION:CM ELT4 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI NEYSHABOURI 
 Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8d6f-cd45-11f1-b6e6-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261022T133000
DTEND;TZID=Europe/Paris:20261022T163000
SUMMARY:Conception des circuits numériques TP (TP04)
DESCRIPTION:TP ELT4 TP04\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c8ee0-cd45-11f1-984a-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261022T093000
DTEND;TZID=Europe/Paris:20261022T123000
SUMMARY:Conception des circuits numériques TP (TP03)
DESCRIPTION:TP ELT4 TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c905d-cd45-11f1-bc8f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261023T120000
DTEND;TZID=Europe/Paris:20261023T123000
SUMMARY:System On Chip (CM01)
DESCRIPTION:CM ELT5 CM01\nAM240 -Amphi B\nMEGHDADI NEYSHABOURI Vahid\n12h00
  - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c91d6-cd45-11f1-b82e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261023T110000
DTEND;TZID=Europe/Paris:20261023T120000
SUMMARY:System On Chip (CM01)
DESCRIPTION:CM ELT5 CM01\nAM240 -Amphi B\nMEGHDADI NEYSHABOURI Vahid\n11h00
  - 12h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c9349-cd45-11f1-9be8-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261104T093000
DTEND;TZID=Europe/Paris:20261104T123000
SUMMARY:Conception des circuits numériques TP (TP03)
DESCRIPTION:TP ELT4 TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c94b4-cd45-11f1-b675-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261105T133000
DTEND;TZID=Europe/Paris:20261105T163000
SUMMARY:Conception des circuits numériques TP (TP04)
DESCRIPTION:TP ELT4 TP04\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c961f-cd45-11f1-837e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261106T133000
DTEND;TZID=Europe/Paris:20261106T163000
SUMMARY:Conception des circuits numériques TP (TP02)
DESCRIPTION:TP ELT4 TP02\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c979d-cd45-11f1-93ba-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261109T150000
DTEND;TZID=Europe/Paris:20261109T170000
SUMMARY:Conception des circuits numériques TP (TP03)
DESCRIPTION:TP ELT4 TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n15h00 - 17h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c990a-cd45-11f1-9afa-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261109T090000
DTEND;TZID=Europe/Paris:20261109T110000
SUMMARY:Conception des circuits numériques TP (TP04)
DESCRIPTION:TP ELT4 TP04\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h00 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c9a7a-cd45-11f1-8426-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261110T080000
DTEND;TZID=Europe/Paris:20261110T093000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c9bf6-cd45-11f1-ab5e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261125T133000
DTEND;TZID=Europe/Paris:20261125T150000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nAM115 -Amphi C\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 15h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c9d65-cd45-11f1-b987-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261125T080000
DTEND;TZID=Europe/Paris:20261125T093000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nSA60 -I122 Salle CIADT\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9c9edb-cd45-11f1-9a8f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261126T110000
DTEND;TZID=Europe/Paris:20261126T123000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA43 -I113\nMEGHDADI NEYSHABOURI 
 Vahid\n11h00 - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca049-cd45-11f1-9ce1-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261201T133000
DTEND;TZID=Europe/Paris:20261201T150000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nSA100 -B4.1 Ex-biblio\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 15h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca1b1-cd45-11f1-924a-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261201T110000
DTEND;TZID=Europe/Paris:20261201T123000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA32 -B11\nMEGHDADI NEYSHABOURI Vahid\n11h00
  - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca34c-cd45-11f1-8a0e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261202T093000
DTEND;TZID=Europe/Paris:20261202T110000
SUMMARY:Mise en œuvre d'un réseau de capteurs (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA42 -C203\nMEGHDADI NEYSHABOURI 
 Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca4bc-cd45-11f1-af5f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261202T080000
DTEND;TZID=Europe/Paris:20261202T093000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nSA100 -B4.1 Ex-biblio\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca624-cd45-11f1-ae8c-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261204T110000
DTEND;TZID=Europe/Paris:20261204T123000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA30 -C206\nMEGHDADI NEYSHABOURI 
 Vahid\n11h00 - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca796-cd45-11f1-ae6e-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261207T110000
DTEND;TZID=Europe/Paris:20261207T123000
SUMMARY:Communications numériques TP 2 (TP03)
DESCRIPTION:TP ELT5 3G TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n11h00 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ca8ff-cd45-11f1-a774-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261207T093000
DTEND;TZID=Europe/Paris:20261207T110000
SUMMARY:Communications numériques TP 2 (TP03)
DESCRIPTION:TP ELT5 3G TP03\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9caa6e-cd45-11f1-badc-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261208T110000
DTEND;TZID=Europe/Paris:20261208T123000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA32 -B11\nMEGHDADI NEYSHABOURI Vahid\n11h00
  - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cabdc-cd45-11f1-9a98-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261208T093000
DTEND;TZID=Europe/Paris:20261208T110000
SUMMARY:Communications numériques TP 2 (TP02)
DESCRIPTION:TP ELT5 3G TP02\nTP -B13 Simul DSP HFSS ADS Matlab 
 (12)\nMEGHDADI NEYSHABOURI Vahid\n09h30 - 11h00\nENSIL\nLast Update 
 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cad47-cd45-11f1-a2df-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261208T080000
DTEND;TZID=Europe/Paris:20261208T093000
SUMMARY:Communications numériques TP 2 (TP02)
DESCRIPTION:TP ELT5 3G TP02\nTP -B13 Simul DSP HFSS ADS Matlab 
 (12)\nMEGHDADI NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 
 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9caeae-cd45-11f1-bea5-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261209T093000
DTEND;TZID=Europe/Paris:20261209T110000
SUMMARY:Mise en œuvre d'un réseau de capteurs (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA32 -B11\nMEGHDADI NEYSHABOURI Vahid\n09h30
  - 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb028-cd45-11f1-be43-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261210T150000
DTEND;TZID=Europe/Paris:20261210T163000
SUMMARY:Communications numériques 2 (TP01)
DESCRIPTION:TP AET5 TP01\nMEGHDADI NEYSHABOURI Vahid\n15h00 - 16h30\nLast 
 Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb1f0-cd45-11f1-a640-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261210T133000
DTEND;TZID=Europe/Paris:20261210T150000
SUMMARY:Communications numériques 2 (TP01)
DESCRIPTION:TP AET5 TP01\nMEGHDADI NEYSHABOURI Vahid\n13h30 - 15h00\nLast 
 Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb35f-cd45-11f1-8a5b-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261210T110000
DTEND;TZID=Europe/Paris:20261210T123000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nAM115 -Amphi C\nMEGHDADI NEYSHABOURI 
 Vahid\n11h00 - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb4d3-cd45-11f1-a2df-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261210T093000
DTEND;TZID=Europe/Paris:20261210T110000
SUMMARY:Communications numériques TP 2 (TP01)
DESCRIPTION:TP ELT5 3G TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb66e-cd45-11f1-8557-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261210T080000
DTEND;TZID=Europe/Paris:20261210T093000
SUMMARY:Communications numériques TP 2 (TP01)
DESCRIPTION:TP ELT5 3G TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb7ed-cd45-11f1-93bf-c0f958618ab4
DTSTART;TZID=Europe/Paris:20261216T080000
DTEND;TZID=Europe/Paris:20261216T100000
SUMMARY:Communication numériques cours 2 (CM01)
DESCRIPTION:CM ELT5 CM01\nCM AET5 CM01\nAM115 -Amphi A\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 10h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cb963-cd45-11f1-8bbe-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270108T090000
DTEND;TZID=Europe/Paris:20270108T120000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h00 - 12h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cbafb-cd45-11f1-967d-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270112T133000
DTEND;TZID=Europe/Paris:20270112T150000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA36 -C207\nMEGHDADI NEYSHABOURI 
 Vahid\n13h30 - 15h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cbc70-cd45-11f1-8771-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270112T093000
DTEND;TZID=Europe/Paris:20270112T110000
SUMMARY:Protocoles (Zegbee\, Iora\, Ble) (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA32 -B11\nMEGHDADI NEYSHABOURI Vahid\n09h30
  - 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cbde0-cd45-11f1-b98d-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270113T133000
DTEND;TZID=Europe/Paris:20270113T163000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cbf5b-cd45-11f1-95a7-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270113T080000
DTEND;TZID=Europe/Paris:20270113T110000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n08h00 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc0cc-cd45-11f1-a029-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270114T133000
DTEND;TZID=Europe/Paris:20270114T180000
SUMMARY:Soutenances projet ELT5A
DESCRIPTION:CM ELT5 CM01\nSA34 -C208\nSA36 -C207\nSA30 -C206\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 18h00\nENSIL\nENSIL\nENSIL\nLast Update 
 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc242-cd45-11f1-96ca-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270118T133000
DTEND;TZID=Europe/Paris:20270118T163000
SUMMARY:Mise en œuvre d'un réseau de capteurs (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc3b7-cd45-11f1-90ab-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270120T093000
DTEND;TZID=Europe/Paris:20270120T113000
SUMMARY:Théorie de l'information (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nSA34 -C208\nMEGHDADI NEYSHABOURI 
 Vahid\n09h30 - 11h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc525-cd45-11f1-a384-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270121T110000
DTEND;TZID=Europe/Paris:20270121T123000
SUMMARY:Simulations et mesures des systèmes de télécoms (CM01)
DESCRIPTION:CM AET5 CM01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n11h00 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc68e-cd45-11f1-b550-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270122T133000
DTEND;TZID=Europe/Paris:20270122T150000
SUMMARY:Bus de communications (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA46 -II110 Salle du Conseil\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 15h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc7f7-cd45-11f1-b3fb-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270125T133000
DTEND;TZID=Europe/Paris:20270125T150000
SUMMARY:Simulations et mesures des systèmes de télécoms (CM01)
DESCRIPTION:CM AET5 CM01\nIN16 -C205 (16)\nMEGHDADI NEYSHABOURI 
 Vahid\n13h30 - 15h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cc95e-cd45-11f1-bc83-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270125T110000
DTEND;TZID=Europe/Paris:20270125T123000
SUMMARY:Bus de communications (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA32 -B11\nMEGHDADI NEYSHABOURI Vahid\n11h00
  - 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ccae4-cd45-11f1-8e6b-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270125T093000
DTEND;TZID=Europe/Paris:20270125T110000
SUMMARY:Simulations et mesures des systèmes de télécoms (CM01)
DESCRIPTION:CM AET5 CM01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ccc53-cd45-11f1-b762-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270126T140000
DTEND;TZID=Europe/Paris:20270126T170000
SUMMARY:Simulations et mesures des systèmes de télécoms (TP01)
DESCRIPTION:TP AET5 TP01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 17h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ccdc9-cd45-11f1-a7d5-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270126T103000
DTEND;TZID=Europe/Paris:20270126T120000
SUMMARY:Bus de communications (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n10h30 - 12h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ccf37-cd45-11f1-956f-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270126T090000
DTEND;TZID=Europe/Paris:20270126T103000
SUMMARY:Bus de communications (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h00 - 10h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd0ba-cd45-11f1-8072-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270127T140000
DTEND;TZID=Europe/Paris:20270127T170000
SUMMARY:Notions avancées (CM01)
DESCRIPTION:CM ELT5 OPT3 CM01\nSA36 -C207\nMEGHDADI NEYSHABOURI 
 Vahid\n14h00 - 17h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd298-cd45-11f1-a3bb-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270127T093000
DTEND;TZID=Europe/Paris:20270127T123000
SUMMARY:Simulations et mesures des systèmes de télécoms (TP01)
DESCRIPTION:TP AET5 TP01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 12h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd409-cd45-11f1-ae46-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270128T103000
DTEND;TZID=Europe/Paris:20270128T120000
SUMMARY:Bus de communications (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n10h30 - 12h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd579-cd45-11f1-b105-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270128T090000
DTEND;TZID=Europe/Paris:20270128T103000
SUMMARY:Bus de communications (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h00 - 10h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd6e9-cd45-11f1-9b31-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270201T133000
DTEND;TZID=Europe/Paris:20270201T163000
SUMMARY:Simulations et mesures des systèmes de télécoms (TP01)
DESCRIPTION:TP AET5 TP01\nIN16 -I112 Salle FISA ELT (16)\nMEGHDADI 
 NEYSHABOURI Vahid\n13h30 - 16h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd85a-cd45-11f1-9efd-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270202T150000
DTEND;TZID=Europe/Paris:20270202T163000
SUMMARY:Soutenance projet
DESCRIPTION:CM AET5 CM01\nSA48 -C11\nMEGHDADI NEYSHABOURI Vahid\n15h00 - 
 16h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cd9c6-cd45-11f1-a46c-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270202T133000
DTEND;TZID=Europe/Paris:20270202T150000
SUMMARY:Soutenance projet
DESCRIPTION:CM AET5 CM01\nSA48 -C11\nMEGHDADI NEYSHABOURI Vahid\n13h30 - 
 15h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cdb2e-cd45-11f1-8b35-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270202T110000
DTEND;TZID=Europe/Paris:20270202T123000
SUMMARY:Soutenance projet
DESCRIPTION:CM AET5 CM01\nSA48 -C11\nMEGHDADI NEYSHABOURI Vahid\n11h00 - 
 12h30\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cdc8e-cd45-11f1-a03b-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270202T093000
DTEND;TZID=Europe/Paris:20270202T110000
SUMMARY:Soutenance projet
DESCRIPTION:CM AET5 CM01\nSA48 -C11\nMEGHDADI NEYSHABOURI Vahid\n09h30 - 
 11h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cddf1-cd45-11f1-8ec0-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270203T140000
DTEND;TZID=Europe/Paris:20270203T153000
SUMMARY:Bus de communications (TP01)
DESCRIPTION:TP ELT5 OPT3 TP01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n14h00 - 15h30\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9cdf5a-cd45-11f1-8e16-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270203T093000
DTEND;TZID=Europe/Paris:20270203T110000
SUMMARY:Codage avancé (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nTP -B04 TP VHDL Logic Design\nMEGHDADI 
 NEYSHABOURI Vahid\n09h30 - 11h00\nENSIL\nLast Update 2026-10-21 
 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ce0c6-cd45-11f1-a935-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270204T080000
DTEND;TZID=Europe/Paris:20270204T093000
SUMMARY:Codage avancé (CM01)
DESCRIPTION:CM ELT5 OPT1 CM01\nTP -B13 Simul DSP HFSS ADS Matlab 
 (12)\nMEGHDADI NEYSHABOURI Vahid\n08h00 - 09h30\nENSIL\nLast Update 
 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ce23e-cd45-11f1-8e8c-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270209T090000
DTEND;TZID=Europe/Paris:20270209T120000
SUMMARY:Codage avancé (TP01)
DESCRIPTION:TP ELT5 OPT1 TP01\nIN30 -C16 (30)\nMEGHDADI NEYSHABOURI 
 Vahid\n09h00 - 12h00\nENSIL\nLast Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ce3b6-cd45-11f1-9309-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270322T133000
DTEND;TZID=Europe/Paris:20270322T173000
SUMMARY:Soutenances projet ELT5A
DESCRIPTION:CM ELT5 CM01\nSA60 -I122 Salle CIADT\nSA46 -II110 Salle du 
 Conseil\nMEGHDADI NEYSHABOURI Vahid\n13h30 - 17h30\nENSIL\nENSIL\nLast 
 Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ce51f-cd45-11f1-bfff-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270322T083000
DTEND;TZID=Europe/Paris:20270322T123000
SUMMARY:Soutenances projet ELT5A
DESCRIPTION:CM ELT5 CM01\nSA60 -I122 Salle CIADT\nSA46 -II110 Salle du 
 Conseil\nMEGHDADI NEYSHABOURI Vahid\n08h30 - 12h30\nENSIL\nENSIL\nLast 
 Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
BEGIN:VEVENT
DTSTAMP:20261021T115313Z
UID:fe9ce68f-cd45-11f1-b85a-c0f958618ab4
DTSTART;TZID=Europe/Paris:20270323T083000
DTEND;TZID=Europe/Paris:20270323T123000
SUMMARY:Soutenances projet ELT5A
DESCRIPTION:CM ELT5 CM01\nSA60 -I122 Salle CIADT\nSA46 -II110 Salle du 
 Conseil\nMEGHDADI NEYSHABOURI Vahid\n08h30 - 12h30\nENSIL\nENSIL\nLast 
 Update 2026-10-21 13:53:13.328995+02:00
END:VEVENT
END:VCALENDAR